Field of the Invention
The present invention relates to a memory, and more particular to the memory with a self-testing mechanism.
Description of the Related Art
Integrated circuits (ICs) have become complex due to increased functionality and high performance. Many ICs include on-chip memory. On-chip memory may take on a variety of forms, for example, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), a non-volatile memory (NVRAM), a flash memory, etc. Among these kinds of memory, random access memory and the read-only memory are most commonly used in the chips, such as a processor, a controller or a digital processing unit (DSP). Since the content stored in a read-only memory cannot be modified, the read-only memory is used to store the main core or main operating system of the chip. The random access memory is normally associated with volatile types of memory, where stored information is lost if power is removed, thus the random access memory usually stores parameters or temporary data generated during an operation of the chip.
Due to the increasing complexity of ICs, additional elements may cause errors on the chip. To avoid shipping defect chips, a testing mechanism is required to find the defective chips. The traditional defect detecting mechanism uses an external ATE (automatic test equipment) to test chips, but it costs time and is not an economical approach. Therefore, another testing mechanism, the Built-in Self Test (BIST), is proposed for some particular circuits, such as a chip with embedded memory. The technique allows the chip to perform a self-testing procedure using additional hardware or software integrated in the chip. The self-testing procedure tests operations (functionally, parametrically, or both) of the chip by using the additional hardware or software of the chip, wherein the software may be stored in the memory. Thus, the new testing mechanism reduces dependence on the external automated test equipment. Although the BIST mechanism provides a relatively efficient approach for chip-testing, however, traditional testing procedures cannot be used for on-the-fly validation or diagnosis. The traditional BIST mechanism needs to be improved.